Freescale Semiconductor StarCore SC140 - Manual (Page 239)

ISAP - SC140 Schematic Connection
SC140 DSP Core Reference Manual 6-59
6.2.2 Multiple ISAP
Connection between the core and multiple ISAPs is illustrated in Figure 6-2, below:
Figure 6-2. Core to Multiple ISAP Connection Schematic
In a multiple ISAP configuration, some of the ISAP instruction encoding bits should be dedicated in
advance for encoding the ISAP selection. For each dispatched ISAP instruction, an ISAP controller
decodes the ISAP select bits and enables the respective ISAP. The other ISAPs are therefore disabled, for
this cycle. The system designer must put these bits in the MSB of the opcode of the ISAP instruction.
Further operation is similar to a single ISAP:
The connections of the ISAPs with the data memory are not shown in Figure 6-2. Proper muxing should be
implemented according to the same principle as shown in Figure 6-1.
ISAP
Core to ISAP
instruction dispatch
ISAP
ISAP
ISAP Controller
IS
A
P
se
le
ct
ion
encod
ing
Enable bits
SC140Core