Freescale Semiconductor StarCore SC140 User Manual
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3-6
SC140 DSP Core Reference Manual
Core Control Registers
SM
Bit 2
Arithmetic Saturation Mode — Selects
automatic saturation on 32 bits for data
arithmetic and logic unit (DALU) results.
This bit provides an arithmetic saturation
mode for algorithms that do not
recognize or cannot take advantage of
the extension register. When the
arithmetic saturation mode is set, the
scaling mode bits are ignored for most
instructions. No scaling is performed.
Refer to
details of arithmetic saturation, including
the list of instructions affected by
arithmetic saturation with or without
scaling.
Each individual instruction in
Appendix A, “SC140 DSP Core
Instruction Set,”
lists arithmetic
saturation as a condition, if appropriate.
This bit is cleared at core reset.
0 = Arithmetic saturation mode not selected
1 = Arithmetic saturation mode selected
T
Bit 1
True Bit — Indicates whether the
condition being tested by a compare or
test instruction is true or false.
The T-bit is affected by all instructions
that check a condition, such as CMPxx,
TSTxx, and BMTSTx. The BMTSET.W
instruction also sets this bit if a write to
memory fails. Conditional instructions
(such as JT, JF, BT, BF, IFT, and others)
test the T-bit, and execute accordingly.
This bit is cleared during core reset as
well as at the start of an exception
service routine.
0 = Condition tested by compare or test instruction is false
1 = Condition tested by compare or test instruction is true
Table 3-1. Status Register Description (Continued)
Name
Description
Settings