Freescale Semiconductor StarCore SC140 - Manual (Page 270)

7-20 SC140 DSP Core Reference Manual
Static Programming Rules
Rule D.2
Core or ISAP instructions that read or write the SR register, affect status bits in SR, or are affected by
status bits in SR are not allowed in a RTED delay slot.
This rule applies to instructions that use the stack pointer SP (implicitly or explicitly) and other stack
pointer OSP, since SR affects which stack pointer is used (EXP status bit).
Example 7-31. Instructions in a RTED Delay Slot
rted
move.l d0,sr
;not allowed
rted
move.l sr,d0
;not allowed
rted
bmset #1,sr.l
;not allowed
rted
rol d0
;not allowed, affected by SR[C]
rted
push d0
;not allowed, affected by SR[EXP]
rted
bmclr.w #64,(sp-8)
;not allowed, affected by SR[EXP]
rted
bmtsts.w #64,(r0)
;not allowed, affects SR[T]
rted
tfra r0,osp
;not allowed, affected by SR[EXP]
rted
tfra sp,r0
;not allowed, affected by SR[EXP]
rted
ift clr d0
;not allowed, affected by SR[T]
rted
tfra r0,r1
;allowed
rted
{tsteq k0}
;changes T bit based on ISAP register - not allowed
rted
bmclr.w #64,(r0)
;allowed
Rule D.3
Core or ISAP instructions that write the SR register or affect status bits in SR cannot be grouped in a VLES
with a RTE/RTED instruction.
Example 7-32. RTE/D with SR Updates
rte add d0,d1,d2 ;not allowed - affects the carry bit in SR
rte {tsteq k0} ;not allowed - affects the T bit in SR