Mpyuu, Fractional multiply, Instruction formats and opcodes – Freescale Semiconductor StarCore SC140 User Manual
Page 643: Operation assembler syntax
MPYUU
SC140 DSP Core Reference Manual
A-329
MPYUU
Fractional Multiply
MPYUU
Unsigned By Unsigned (DALU)
Description
Status and Conditions that Affect Instruction
None.
Status and Conditions Changed by Instruction
Example
mpyuu d4,d5,d6
0.010
$2000 (2
–2
)
x 0.100$4000 (2
–1
)
0.001
$1000 (2
–3
)
Instruction Formats and Opcodes
Note:
** indicates serial grouping encoding.
Operation
Assembler Syntax
Dc.L * Dd.L
→ Dn
MPYUU Dc,Dd,Dn
MPYUU Dc,Dd,Dn
Performs unsigned fractional multiplication between the unsigned 16-bit LP of the first register (Dc) of a data register
pair with the unsigned 16-bit LP of the second register (Dd). It then stores the sign-extended 32-bit product in a
destination data register (Dn).
Register Address
Bit Name
Description
Ln
L
Clears the Ln bit in the destination registers.
Register/Memory Address
Before
After
D4
$00 4000 2000
D5
$FF E000 4000
L6:D6
$0:$00 1000 0000
Instruction
Words Cycles Type
Opcode
15
8
7
0
MPYUU Dc,Dd,Dn
1
1
1
0
*
1
0
1
1
F
F
F
1
1
0
1
1
e
e