Freescale Semiconductor StarCore SC140 - Manual (Page 181)

SC140 DSP Core Reference Manual 5-1
Chapter 5
Program Control
This chapter describes the program control features for the SC140 including:
• Pipeline
• Instruction grouping
• Instruction timing
• Hardware loops
• Stack support
• Processing states
• Exception processing
The SC140 core, being a multiple ALU processor, has special hardware that can issue up to two AGU and
four DALU instructions at the same time. When two or more instructions are being issued to two or more
execution units in the same clock cycle, these instructions are defined as grouped. The C compiler or the
assembly programmer can specify in the source code which instructions are grouped together according to
the SC140 programming rules. When the assembler compiles the DSP code, it specifies in the encoding
whether an instruction stands alone, or whether it is grouped with other instructions. In each clock cycle,
the dispatch logic detects how many instructions are grouped. Each group of instructions issued to the
execution units on a given clock cycle is called an execution set. Each line of eight words read from the
program memory and associated with an address is called a fetch set.
5.1 Pipeline
This section describes how instructions are processed in the SC140 core pipeline. The SC140 pipeline
consists of five stages:
• Pre-fetch stage
• Fetch stage
• Dispatch stage
• Address generation stage
• Execution stage
The first three stages are implemented in the program sequencer unit (PSEQ). The last two stages are
implemented in the AGU and DALU, respectively.