Freescale Semiconductor StarCore SC140 - Manual (Page 228)

5-48 SC140 DSP Core Reference Manual
Exception Processing
3. The PSEQ services an exception request when ready, typically in five cycles. It may
postpone an exception while a change-of-flow is executing (up to 16 cycles latency). After
fetching an exception service routine base address, the core enters the exception working
mode. The next PC value (namely, the address of the execution set where execution should
be resumed upon the return from the exception) is pushed onto the exception stack together
with the SR. The instruction set at the exception vector address associated with the selected
exception is fetched. This address is formed as follows:
— Bits 31:12 from the Vector Base Address Register (VBA)
— Bits 11:6 from either the exception and interrupt address offset table (Table 5-19) or the external
Interrupt Offset Bus as enabled by the AUTO_VEC signal and an external interrupt. External
interrupts with a default vector address (indicated by the AUTO_VEC signal) refer to the
AUTO-NMI and AUTO-IR vectors in Table 5-19.
— Bits 5:0 of an exception vector base address are always zero, allowing 16 bytes at each vector.
— The first three execution sets from the fetched exception vector enter execution. Only then can
a new exception request be serviced.
5.8.1 Interrupt Vector Address
5.8.1.1 Vector Base Address Register
The Vector Base Address Register (VBA) is a 32-bit register with the lower 12 bits always zero. The upper
twenty bits [31:12] are automatically used to form the base address (bits [31:12] of the exception vector
address). The upper twenty bits of VBA are initialized at reset with a derivative-dependent address
pointing to the initial Vector Address Table. After reset, VBA may be programmed to relocate the Vector
Address Table anywhere in memory. Care must be taken that interrupts are disabled (either in the core or
in the system) when changing the VBA register, otherwise an interrupt serviced during the change process
may use either the old or new VBA value.
5.8.1.2 Programming Exception Routine Addresses
Each exception vector address is formed from a base address and an offset. The base address bits [31:12]
come from the VBA register. Bits 11:6 of the offset are from either the exception vector address table
(Table 5-19) or the external Interrupt Offset Bus as enabled by the AUTO_VEC signal and an external
interrupt. External interrupts with a default vector address (indicated by the AUTO_VEC signal) refer to
the AUTO-NMI and AUTO-IR vectors in Table 5-19. Bits [5:0] are zero since the distance between two
exception vectors is 16 bytes (one full execution set). There are 64 possible exception vector locations in
the table.
Table 5-19 shows the exception vector address offsets. The last row in the table is for offsets from 0x200 to
0xFC0. These can be accessed by either the non-maskable interrupt or the (maskable) external interrupt,
since the user-driven Interrupt Offset bus determines this address for either type.