Clear a data register (dalu), Instruction formats and opcodes, Operation assembler syntax – Freescale Semiconductor StarCore SC140 User Manual
Page 429: Clr d1
CLR
SC140 DSP Core Reference Manual
A-115
CLR
Clear a Data Register (DALU)
CLR
Description
Status and Conditions that Affect Instruction
None.
Status and Conditions Changed by Instruction
Example
clr d1
Instruction Formats and Opcodes
Note:
** indicates serial grouping encoding.
Operation
Assembler Syntax
0
→ Dn
CLR Dn
CLR Dn
Clears a data register (Dn).
Note:
CLR Dn is assembler mapped to SUB Da,Da,Dn where Dn is the register being cleared and Da is
an arbitrary register assigned by the assembler for programming rule G.G.5. Any (Da-Da) results in
zero being stored in Dn. Da assignment uses the low data registers (D0-D7) where possible to avoid
using a prefix.
Register Address
Bit Name
Description
Ln
L
Clears the Ln bit in the destination register.
SR[0]
C
Clears the carry bit.
Register/Memory Address
Before
After
SR
$00E0 0001
$00E0 0000
L1:D1
$0:$00 0000 0040
$0:$00 0000 0000
Instruction
Words Cycles Type
Opcode
15
8
7
0
CLR
Dn (Da even)
1
1
1
0
*
1
0
1
1
F
F
F
0
0
J
J
J
J
J
CLR
Dn (Da odd)
1
1
1
0
*
1
0
0
0
F
F
F
1
1
0
0
1
j
j