Freescale Semiconductor StarCore SC140 - Manual (Page 547)

MAC
SC140 DSP Core Reference Manual A-233
MAC
Signed Fractional Multiply-Accumulate (DALU)
MAC
Description
These operations perform signed fractional multiplication of two 16-bit signed operands (Da.H and Db.H).
They then add or subtract the product to or from a data register (Dn). One operand is the HP of a data
register. The other operand is either the HP of a data register or an immediate 16-bit signed data.
Status and Conditions that Affect Instruction
Status and Conditions Changed by Instruction
Example 1
mac d4,d5,d6
Operation Assembler Syntax
Dn + (#s16 * Da.H)
→ Dn
MAC #s16,Da,Dn {–2 15
≤ s16 < 2
15 }
Dn
± (Da.H * Db.H) → Dn
MAC
±Da,Db,Dn
MAC #s16,Da,Dn
Adds the product of an immediate 16-bit word and a data register (Da) to the destination register (Dn).
MAC
±Da,Db,Dn
Multiplies the HP contents of two data registers (Da, Db) and adds or subtracts the product to or from a
destination data register (Dn). The default is to add the product to the destination register.
Register Address Bit Name Description
SR[2] SM If set, selects 32-bit arithmetic saturation mode.
SR[5:4] S[1:0] Scaling mode bits determine which bits in the result are used in the
Ln bit calculation.
Register Address Bit Name Description
Ln L If not in arithmetic saturation mode (SR [SM] = 0), calculates and
updates the Ln bit in the destination register. If in arithmetic
saturation mode (SR [SM] = 1), clears the Ln bit in the destination
register.
EMR[2] DOVF Set if the result cannot be represented in 40 bits, or if the result
saturates to 32 bits in arithmetic saturation mode.
Register/Memory Address Before After
SR $00E0 0000
D4 $00 1000 0000