Freescale Semiconductor StarCore SC140 - Manual (Page 740)

A-426 SC140 DSP Core Reference Manual
WAIT
WAIT
Wait for an Interrupt (AGU)
WAIT
Description
Operation Assembler Syntax
Enters the low-power standby WAIT processing
state. WAIT
WAIT
Enters the low-power standby WAIT processing state. All internal core processing is halted until an
unmasked interrupt occurs, the DSP is reset, the EE0 is asserted, or a JTAG debug request command is
issued. If an exit from the WAIT processing state is caused by asserting EE0 or the JTAG debug request
command, the processor enters the debug state immediately.
The WAIT processing state is intended to be an intermediate power consumption mode between the
execution processing state and the STOP processing state. The decision what parts of the system other than
the core will have their clocks shut down in the WAIT processing state and what parts will continue to
operate is system dependent. Common examples are peripherals that might receive data and memories that
can be accessed by DMA controllers, which interrupt the core when data is available for processing.
The WAIT instruction can appear only once in an execution set.
During the WAIT processing state, if a maskable interrupt is asserted, the core behaves according to the
following rules:
Condition Response
The priority level of the interrupt is higher than the
level programmed in the
SR by the IPLn bits, and the
DI bit in SR is clear (meaning the interrupt is enabled).
Exit the WAIT state and service the interrupt immediately
after the execution set that included the WAIT instruction.
The priority level of the interrupt is higher than the
level programmed in the
SR by the IPLn bits, and the
DI bit in SR is set (meaning the interrupt is masked
only by the DI bit).
Exit the WAIT state and continue execution of the execu-
tion set that included the WAIT instruction. Do not jump to
the interrupt service routine.
The priority level of the interrupt is lower than or equal
to the level programmed in the
SR by the IPLn bits.
Remain in the WAIT state.
A non-maskable interrupt is asserted. Exit the WAIT state and service the non-maskable interrupt
immediately after the execution set that included the WAIT
instruction, regardless of the value of the IPL and DI bits in
the
SR .