Mpysu, Fractional multiply, Instruction formats and opcodes – Freescale Semiconductor StarCore SC140 User Manual
Page 639: Instruction fields, Operation assembler syntax
MPYSU
SC140 DSP Core Reference Manual
A-325
MPYSU
Fractional Multiply
MPYSU
Signed By Unsigned (DALU)
Description
Status and Conditions that Affect Instruction
None.
Status and Conditions Changed by Instruction
Example
mpysu d4,d5,d6
Instruction Formats and Opcodes
Note:
** indicates serial grouping encoding.
Instruction Fields
Dc,Dd
ee
Data Register Pairs
Operation
Assembler Syntax
Dc.H * Dd.L
→ Dn
MPYSU Dc,Dd,Dn
MPYSU Dc,Dd,Dn
Performs signed fractional multiplication between the signed 16-bit HP of the first register (Dc) of a data
register pair with the unsigned 16-bit LP of the second register (Dd). It then stores the sign-extended 32-bit
product in a destination data register (Dn).
Register Address
Bit Name
Description
Ln
L
Clears the Ln bit in the destination registers.
Register/Memory Address
Before
After
D4
$FF C000 0001
D5
$FF E000 0002
L6:D6
$0:$FF FFFF 0000
Instruction
Words Cycles Type
Opcode
15
8
7
0
MPYSU
Dc,Dd,Dn
1
1
1
0
*
1
0
1
1
F
F
F
1
1
0
1
0
e
e
00
D0,D1
01
D2,D3
10
D4,D5
11
D6,D7
Note:
This instruction can specify D8-D15 as operands by using a prefix.