Freescale Semiconductor StarCore SC140 - Manual (Page 465)

DIV
SC140 DSP Core Reference Manual A-151
Status and Conditions that Affect Instruction
Status and Conditions Changed by Instruction
Example
div d2,d1
3. Calculate the next quotient bit and the new partial remainder: The 16-bit signed divisor
in Da.H is either added to or subtracted from Dn.H, and the result is stored back into Dn.H.
If the result of the exclusive OR operation previously described was a “1” (i.e., the sign bits
were different), Da.H is added to Dn.H. If the result of the exclusive OR operation was a “0”
(i.e., the sign bits were the same), Da.H is subtracted from Dn.H. Because of the
sign-extension of the 16-bit signed divisor, the addition or subtraction operation correctly
sets the carry bit C of the condition code register with the next quotient bit.
For extended precision division (i.e., for N-bit quotients where N>16), the DIV instruction is no longer
applicable, and a user-defined N-bit division routine is required.
For further information on division algorithms, refer to pages 524–530 of Theory and Application of
Digital Signal Processing by Rabiner and Gold (Prentice-Hall, 1975), pages 190–199 of Computer
Architecture and Organization by John Hayes (McGraw-Hill, 1978), pages 213–223 of Computer
Arithmetic: Principles, Architecture, and Design by Kai Hwang (John Wiley and Sons, 1979), or other
references as required.
Register Address Bit Name Description
SR[0] C Carry bit is copied into Dn[0].
SR[5:4] S[1:0] Scaling mode bits determine which bits in the result are used in the Ln
bit calculation.
Register Address Bit Name Description
SR[0] C Bit is set if bit 39 of the result is cleared.
EMR[2] DOVF Set if the MS bit of the result cannot be represented in 40 bits, or is
changed as a result of the instruction’s left shift operation.
Ln L Calculates and updates the Ln bit in the destination register.
Register/Memory Address Before After
D2 $00 2311 5A3B
L1:D1 $0:$00 6666 0A57 $0:$00 A9BB 14AE
SR $00E4 0000 $00E4 0001
EMR $0000 0000