Freescale Semiconductor StarCore SC140 - Manual (Page 332)

A-18 SC140 DSP Core Reference Manual
DSP Core Instruction Set
RTED Return from exception (delayed)
RTS Return from subroutine
RTSD Return from subroutine (delayed)
RTSTK Force restore PC from the stack, updating SP
RTSTKD Force restore PC from the stack, updating SP (delayed)
TRAP Execute a precise software exception
Table A-14. AGU Loop Control (Including Loop COF) Instructions
Instruction Description
BREAK Terminate the loop and branch to an address
CONT Jump to the start of the loop to start the next iteration
CONTD Jump to the start of the loop to start the next iteration (delayed)
DOENn Do enable - set loop counter n and enable loop n as a long loop
DOENSHn Do enable short - set loop counter n and enable loop n as a short loop
DOSETUPn Setup loop start address n
SKIPLS Test the active LC and skip the loop if LCn is equal or smaller than zero
Table A-15. AGU Program Control Instructions
Instruction Description
DEBUG Enter debug mode
DEBUGEV Signal debug event
DI Disable interrupts (sets the DI bit in the status register)
EI Enable interrupts (clears the DI bit in the status register)
ILLEGAL Trigger an imprecise illegal instruction exception
MARK Push the PC into the trace buffer
STOP Stop processing (lowest power stand-by)
WAIT Wait for interrupt (low power stand-by)
Table A-16. Prefix Instructions
Instruction Description
IFA Execute current execution set or subgroup unconditionally
IFF Execute current execution set or subgroup if the T bit is clear
IFT Execute current execution set or subgroup if the T bit is set
NOP No operation
Table A-13. AGU Non-Loop Change-of-Flow Instructions
Instruction Description