8 programming rules, 1 isap functions that interact with the core, Programming rules -67 – Freescale Semiconductor StarCore SC140 User Manual
Page 247: Isap functions that interact with the core -67
Programming Rules
SC140 DSP Core Reference Manual
6-67
line 1: The ift (if true) prefix instruction indicates that the core MAC instructions will be executed only if
the T bit is set.
lines2,3,4: The iff (if false) prefix instruction indicates that the ISAP instructions on lines 2,3 (including
the implicit MOVE generated for the move_special ISAP instruction) and the core MOVE.L instruction
on line 4 will be executed if the T bit is cleared.
6.8 Programming Rules
This section overviews all SC140 programming rules that relate to ISAP instructions. These programming
rules also appear in
Chapter 7, “Programming Rules,”
but are briefly summarized here as well.
ISAP-specific programming rules depend on the specific ISAP application should be described in the
specific ISAP specification document, and are out of the scope of this document.
6.8.1 ISAP Functions that Interact With the Core
The functionality of ISAP instructions is in principle free to be defined as the ISAP architect wishes.
However, some ISAP functions use core resources or affect core state. These functions usually have
limitations associated with them, as will be described in the following sections:
•
Read data from the data memory to ISAP register(s). An implicit SC140 AGU MOVE instruction is
needed for this function.
•
Write data from to ISAP register(s) to the data memory. An implicit SC140 AGU MOVE instruction
is needed for this function.
•
Exchange data between core registers and ISAP register(s). An implicit SC140 AGU MOVE
instruction is needed for this function.
•
Accept immediate data from the core into ISAP register(s). An implicit SC140 AGU MOVE
instruction is needed for this function.
•
Change the value of the SC140 core T bit in SR
•
ISAP instructions could be predicated with the IFT/IFF prefix instructions like other core
instructions.
In addition, there are other guidelines, as follows:
•
ISAP instructions must have the same semantics of parallel execution like core instructions (for
example destination operands do not affect source operands in the same VLES, etc.). In general, the
guidelines as written in Sections 7.1 VLES Sequencing Semantics through 7.3 SC140 Pipeline
Exposure must be adhered to.
•
The ISAP’s pipeline should be coupled to the SC140 core, which means that instructions that
perform data memory accesses or data processing should have similar pipeline behavior like
respective SC140 core AGU or DALU instructions. For a description on the SC140 pipeline, see