Freescale Semiconductor StarCore SC140 - Manual (Page 231)

Exception Processing
SC140 DSP Core Reference Manual 5-51
If two or more exceptions are pending on the same clock cycle, the one with the higher priority (as defined
in Table 5-19 on page 5-49) is taken.
Due to the imprecise nature of these exceptions, there may be additional exception events between the first
event and its exception service routine. Additional exception events will set their associated EMR bits and
be serviced according to their exception priority, not necessarily according to the order of the execution
sets that caused them.
5.8.5.1 Illegal Exception
The illegal exception is generated by any of several conditions, described in the following sections. To
enable application developers to debug applications and avoid illegal conditions and errors, the SC140
core provides exception bits in the EMR, which are set when an exception is detected. The EMR is
described in detail in
Section 3.1.2, “Exception and Mode Register (EMR).” the address of the execution
set that caused the last Illegal exception is written to the PC_EXCP register of the EOnCE.
5.8.5.1.1 Illegal Instruction
An illegal instruction exception is generated when one or more of the instruction opcodes coming from the
program memory do not belong to the SC140 instruction set. This exception can also be generated by the
ILLEGAL instruction. To prevent the system from entering a deadlock state whenever there is an illegal
instruction, an internal exception request is generated, and the ILIN bit in the EMR is set. The execution
flow continues until the exception is serviced. Execution of the original program is undefined.
The ILIN bit does not block subsequent illegal instruction exceptions. Multiple illegal instructions will
cause multiple illegal exceptions, regardless of the ILIN state. However, illegal instructions that occur
close together may share the same illegal exception. In particular, additional illegal events that occur
between the first event and its illegal exception service routine will share the same exception. If an illegal
execution set also occurred during this period, the ILST bit in EMR will be set to indicate multiple causes
for this illegal exception. If the illegal exception service routine has an illegal instruction, nested illegal
exceptions will occur.
5.8.5.1.2 Illegal Execution Set
An illegal execution set exception is generated whenever one of the following execution set grouping rules
is violated:
• A maximum of four DALU instructions per set can occupy different modulo four positions within
the set.
• A maximum of two AGU instructions per set can occupy different modulo two positions within
the set.
• A maximum of two extension words per set can occupy different modulo two positions within the
set.
• A maximum of one ISAP instruction is allowed per set.
Whenever an illegal set occurs, an exception request is generated. The ILST bit in the EMR is set, and
instruction execution continues until the exception is serviced. Execution of the original program code is
undefined after this exception occurs.
The ILST bit does not block subsequent illegal execution set exceptions. Multiple illegal execution sets
will cause multiple illegal exceptions, regardless of the ILST state. However, illegal execution sets that
occur close together may share the same illegal exception. In particular, additional illegal events that occur
between the first event and its illegal exception service routine will share the same exception. If an illegal