Freescale Semiconductor StarCore SC140 - Manual (Page 95)

Memory Interface
SC140 DSP Core Reference Manual 2-63
Figure 2-25 shows the memory accesses to the same memory area by both program fetches as well as data
accesses in big and little endian modes.
Figure 2-25. Instruction Moves in Big and Little Endian Modes
The Program Bus contents always appear as eight 16-bit little endian packed instructions, the memory
system performing a word (instruction) reversal in the case of big endian (program bus only).
0
8
16 ($10)
7 6 5 4 3 2 1 0
0
8
16 ($10)
0 1 2 3 4 5 6 7
Little Endian Big Endian
a0b0 c0d0 e0f0 a1b1
c1d1 e1f1 a2b2 c2d2
e2f2 a3b3 c3d3 e3f3
a1b1 e0f0 c0d0 a0b0
c2d2 a2b2 e1f1 c1d1
e3f3 c3d3 a3b3 e2f2
Memory
MOVE.4W from address $00
MOVE.L from address $08
64-
bit XB-BUS
64-
bit XA-BUS
Instructions Data Bus Contents Data Bus Contents
64-b
it XB-BUS
64-
bit XA-BUS
SC140 Core
128-b
it P-BUS
c2d2_a2b2_e1f1_c1d1_a1b1_e0f0_c0d0_a0b0
Memory System Changes Big Endian to Little
a1b1_e0f0_c0d0_a0b0
xxxx_xxxx_e1f1_c1d1
Program Bus Contents (for both Endian cases)
FETCH (always 128 aligned) from address A0
MOVE.W from address $08
xxxx_xxxx_xxxx_c1d1
MOVE.B from address $08
xxxx_xxxx_xxxx_xxd1
a0b0_c0d0_e0f0_a1b2
xxxx_xxxx_c1d1_e1f1
xxxx_xxxx_xxxx_c1d1
xxxx_xxxx_xxxx_xxc1