Freescale Semiconductor StarCore SC140 - Manual (Page 172)

4-62 SC140 DSP Core Reference Manual
Event Selector (ES) Registers
Figure 4-23 displays the bit configuration of ESEL_CTRL.
The shaded bits are reserved and should be initialized with zeros for future software compatibility.
Figure 4-23. Event Selector Control Register (ESEL_CTRL)
The ESEL_CTRL fields are described in Table 4-21.
Each of the following event selector registers can enable the system to configure what debug events
(EDCA event, EE event etc.) will cause the outcome controlled by that register (entry into debug state,
debug exception etc.).
BIT 7 6 5 4 3 2 1 BIT 0
SELDTB SELETB SEDLDI SELDM
TYPE rw rw rw rw rw rw rw rw
RESET 0 0 0 0 0 0 0 0
Table 4-21. ESEL_CTRL Description
Name Description Settings
R
Bits 7–5 Reserved
SELDTB
Bit 4 Selection Bit for Trace Disable —
Determines how the enabled sources
disable trace. 0 = Trace is disabled upon detection of the event by any one
of the sources (ORed) selected on the ESEL_DTB
register.
1 = Trace is disabled upon detection of the event by all the
sources (ANDed) selected on the ESEL_DTB register.
SELETB
Bit 3 Selection Bit for Trace Enable —
Determines how the enabled sources
enable trace. 0 = Trace is enabled upon detection of the event by any one
of the sources (ORed) selected on the ESEL_ETB
register.
1 = Trace is enabled upon detection of the event by all the
sources (ANDed) selected on the ESEL_ETB register.
R
Bit 2 Reserved
SELDI
Bit 1 Selection Bit for Debug Exception —
Determines how the enabled sources
cause a debug exception. 0 = A debug exception is reached upon detection of the
event by any one of the sources (ORed) selected on the
ESEL_DI register.
1 = A debug exception is reached upon detection of the
event by all the sources (ANDed) selected on the
ESEL_DI register.
SELDM
Bit 0 Selection Bit for Debug state —
Determines how the enabled sources
cause the core to enter into debug state. 0 = Core enters debug state upon detection of the event by
any one of the sources (ORed) selected on the
ESEL_DM register.
1 = Core enters debug state upon detection of the event by
all the sources (ANDed) selected on the ESEL_DM
register.