Freescale Semiconductor StarCore SC140 - Manual (Page 163)

Event Counter Registers
SC140 DSP Core Reference Manual 4-53
4.8.3 Extension Counter Value Register (ECNT_EXT)
This is a 32-bit register that is used in the extended mode of operation to count the number transitions from
1 to 0 in the ECNT_VAL register. See
Section 4.5.2, “Event Counter,” for further details. The ECNT_EXT
register counts up. Reset writes zeros to this register. Software can write the register when new counting is
started. The MSB is always zero, so the count is from $0000 0000 to $7FFF FFFF. When the register is
written, the MSB should be written to zero for software compatibility.
4.8.4 EC Signals
The two event counter signals EC0 and EC1 allow the event counter to count off-core events such as cache
hits/misses, memory contention, external wait states, etc. These inputs are assumed to be synchronized to
the core clock and support a counting rate up to the core frequency. EC0 and EC1 use is
derivative-dependent.