Freescale Semiconductor StarCore SC140 - Manual (Page 115)

Overview of the Combined JTAG and EOnCE Interface
SC140 DSP Core Reference Manual 4-5
Figure 4-2. TAP Controller State Machine
At power-up or during normal operation of the host, the TAP is forced into the Test-Logic-Reset state
when the
TMS signal is driven high for five or more Test Clock (TCK) cycles.
When test access is required, TMS is set low to cause the TAP to exit the Test-Logic-Reset and move
through the appropriate states. From the Run-Test/Idle state, an instruction register scan or a data register
scan can be issued to transition through the appropriate states.
Table 4-3. JTAG Scan Paths
Select-DR Scan Path Select-IR Scan Path
Select-DR_SCAN Select-IR_SCAN
Capture-DR Capture-IR
Shift-DR Shift-IR
Exit1-DR Exit1-IR
Update-DR Update-IR
Test-Logic-Reset
Run-Test/Idle Select-DR-Scan
Capture-DR
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
Update-DR
Select-IR-Scan
Capture-IR
Shift-IR
Exit1-IR
Pause-IR
Exit2-IR
Update-IR
TMS=1
TMS=0
TMS=0
TMS=0
TMS=0
TMS=0
TMS=0
TMS=0 TMS=0
TMS=0 TMS=0
TMS=0 TMS=0
TMS=0 TMS=0
TMS=1
TMS=1 TMS=1
TMS=1 TMS=1
TMS=1
TMS=1
TMS=1
TMS=1
TMS=0 TMS=0
TMS=1 TMS=1
TMS=1 TMS=1
TMS=1 TMS=1