Freescale Semiconductor StarCore SC140 - Manual (Page 348)

A-34 SC140 DSP Core Reference Manual
ADDL2A
ADDL2A
Add With Two-Bit Arithmetic Shift Left
ADDL2A
of Source Operand (AGU)
Description
Status and Conditions that Affect Instruction
Status and Conditions Changed by Instruction
None.
Example
addl2a r0,r1
In binary:
Operation Assembler Syntax
(rx<<2) + Rx
→ Rx
ADDL2A rx,Rx
ADDL2A rx,Rx
Performs a two-bit arithmetic shift left on the data from AGU source register (rx), adds the result to another
AGU source register (Rx), and stores the sum in the destination (second) register (Rx). For R0-R7
destinations, the operation is affected by the modifier mode selected in MCTL.
Register Address Bit Name Description
SR[18] EXP Determines which stack pointer is used when the stack pointer is an
operand. Otherwise, the instruction is not affected by SR.
MCTL[31:0] AM3–AM0 Address modification bits when updating R0–R7. Otherwise, the
instruction is not affected by MCTL.
Register/Memory Address Before After
MCTL $0000 0000
R0 $0000 0055
R1 $0000 0011 $0000 0165
R0 0101 0101
R0 shifted left two 1 0101 0101
R1 0001 0001
Sum 1 0110 0101