Freescale Semiconductor StarCore SC140 - Manual (Page 492)

A-178 SC140 DSP Core Reference Manual
ILLEGAL
ILLEGAL
Generate an Illegal Exception
ILLEGAL
Request (AGU)
Description
Operation Assembler Syntax
upon service: PC
→ (ESP); SR → (ESP + 4);
SP + 8
→ SP; VBA[31:12]: illegal_vector → PC;
1
→ EXP
111
→ I[2:0]
1
→ ILIN
0
→ C
0 → T
00
→ S[1:0]
0
→ SLF
0000
→ LF[3:0]
ILLEGAL {illegal vector = $080}
ILLEGAL
Generates an imprecise non-maskable illegal exception request. The exact place in the execution
flow that the request is serviced depends on the machine state. Imprecise means that the exception
timing is not guaranteed, being asynchronous with the instruction execution. Users should not rely
on any timing between the ILLEGAL instruction execution and the start of exception processing.
In the most common case, the exception vector is executed after four more execution sets are
executed following the illegal instruction. In other cases, it can be the set immediately after or
delayed by another execution set. Thus, it should be realized that in the exception routine, the
machine state cannot be reconstructed to the exact state before or after the ILLEGAL instruction
is executed. It is possible, however, to know at which PC the request was raised by reading the
PC_EXCP register in the EOnCE (see the EOnCE section for a description of this register).
The AGU sets the EXP bit in SR to switch the active stack pointer to the exception stack pointer. .