16550 uart, Core overview, Feature description – Altera Embedded Peripherals IP User Manual
Page 87: 16550 uart -1, Core overview -1, Feature description -1
16550 UART
9
2014.24.07
UG-01085
Core Overview
The Altera 16550 UART (Universal Asynchronous Receiver/Transmitter) soft IP core with Avalon
interface is designed to be register space compatible with the de-facto standard 16550 found in the PC
industry. The core provides RS-232 Signaling interface, False start detection, Modem control signal and
registers, Receiver error detection and Break character generation/detection. The core also has an Avalon
Memory-Mapped (Avalon-MM) slave interface that allows Avalon-MM master peripherals (such as a
Nios
®
II processor) to communicate with the core simply by reading and writing control and data
registers.
The 16550 UART requires device families with MLABs to run. The recommended device family is series
V and above.
Feature Description
The 16550 Soft-UART has the following features:
• RS-232 signaling interface
• Avalon-MM slave
• Single clock
• False start detection
• Modem control signal and registers
• Receiver error detection
• Break character generation/detection
Table 9-1: UART Features and Configurability
Features
Run Time Configurable
Generate Time Configurable
FIFO/FIFO-less mode
Yes
Yes
FIFO Depth
-
Yes
5-8 bit character length
Yes
-
1, 1.5, 2 character stop bit
Yes
-
Parity enable
Yes
-
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