Altera Embedded Peripherals IP - Manual (Page 336)

IP Caveats
There are limitations in the Altera interrupt latency which the user needs to be aware of. This limitation
arises due to the nature of state machines which incurs a period of clock cycle for state transitions.
1. The data latency registers cannot be read before a first IRQ is fired in any of the 32 channels. This
causes the Waitrequest signal to be perpetually high which would lead to a system stall.
2. The data registers can only be read three clock cycles after the counter registers stop counting. These
three clock cycles originate from the state machine moving from the start state to the stop/store state.
It takes an additional clock cycle to propagate the data from the counter registers to the data store
registers.
3. In the pulse IRQ mode, there is an idle cycle present between two consecutive write commands into
the counter stop register. So, in the event that channel 1 is halted immediately after channel 0 is halted,
then the minimum difference you see in the registered values is 2.
Document Revision History
Table 34-9: Document Revision History
Date and
Document
Version
Changes Made Summary of Changes
July 2014
v14.0 - Initial Release
34-8 IP Caveats
UG-01085
2014.24.07
Altera Corporation Altera Interrupt Latency Counter
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