On-chip fifo memory core, Core overview, Functional description – Altera Embedded Peripherals IP User Manual
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On-Chip FIFO Memory Core
16
2014.24.07
UG-01085
Core Overview
The on-chip FIFO memory core buffers data and provides flow control in an Qsys Builder system. The
core can operate with a single clock or with separate clocks for the input and output ports, and it does not
support burst read or write.
The input interface to the on-chip FIFO memory core may be an Avalon
®
Memory Mapped (Avalon-
MM) write slave or an Avalon Streaming (Avalon-ST) sink. The output interface can be an Avalon-ST
source or an Avalon-MM read slave. The data is delivered to the output interface in the same order that it
was received at the input interface, regardless of the value of channel, packet, frame, or any other signals.
In single-clock mode, the on-chip FIFO memory core includes an optional status interface that provides
information about the fill level of the FIFO core. In dual-clock mode, separate, optional status interfaces
can be included for the input and output interfaces. The status interface also includes registers to set and
control interrupts.
Device drivers are provided in the HAL system library allowing software to access the core using ANSI C.
Functional Description
The on-chip FIFO memory core has four configurations:
• Avalon-MM write slave to Avalon-MM read slave
• Avalon-ST sink to Avalon-ST source
• Avalon-MM write slave to Avalon-ST source
• Avalon-ST sink to Avalon-MM read slave
In all configurations, the input and output interfaces can use the optional backpressure signals to
prevent underflow and overflow conditions. For the Avalon-MM interface, backpressure is
implemented using the
waitrequest
signal. For Avalon-ST interfaces, backpressure is implemented
using the
ready
and
valid
signals. For the on-chip FIFO memory core, the delay between the sink
asserts
ready
and the source drives valid data is one cycle.
Avalon-MM Write Slave to Avalon-MM Read Slave
In this configuration, the input is a zero-address-width Avalon-MM write slave. An Avalon-MM write
master pushes data into the FIFO core by writing to the input interface, and a read master (possibly the
same master) pops data by reading from its output interface. The input and output data must be the same
width.
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