Altera msi to gic generator, Overview, Background – Altera Embedded Peripherals IP User Manual
Page 320: Feature description, Altera msi to gic generator -1, Overview -1, Background -1, Feature description -1
Altera MSI to GIC Generator
33
2014.24.07
UG-01085
Overview
In the PCI subsystem, Message Signaled Interrupts (MSI) is a feature that enables a device function to
request service by writing a system-specified data value to a system-specified message address (using a
PCI DWORD memory write transaction). System software initializes the message address and message
data during device configuration, allocating one or more system-specified data and system-specified
message addresses to each MSI capable function.
A MSI target (receiver), Altera PCIe RootPort Hard IP, receives MSI interrupts through the Avalon-ST
RX TLP of type MWr. For Avalon-MM based PCIe RootPort Hard IP, the RP_Master issues a write
transaction with the system-specified message data value to the system-specified message address of a MSI
TLP received. This memory mapped mechanism does not issue any interrupt output to host the
processor; and it relies on the host processor to poll the value changes at the system-specified message
address in order to acknowledge the interrupt request and service the MSI interrupt. This polling
mechanism may overwhelm the processor cycles and it is not efficient.
The Altera MSI-to-GIC Generator is introduced with the purpose of allowing level interrupt generation to
the host processor upon arrival of a MSI interrupt. It exists as a separate module to Altera PCIe HIP for
completing the interrupt generation to host the processor upon arrival of a MSI TLP.
Background
The existing implementation of the MSI target at Altera PCIe RootPort translates the MSI TLP received
into a write transaction via PCIe Hard IP Avalon-MM Master port (RP_Master). No interrupt output
directed to the host processor to kick start the service routine for the MSI sender is needed.
Feature Description
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