Altera Embedded Peripherals IP - Manual (Page 198)

• In memory-to-memory configurations, the DMA read block receives the source address from its
command FIFO and starts reading data to fill the FIFO on its stream port until the specified
number of bytes are transferred. The DMA read block pauses when the FIFO is full until the FIFO
has enough space to accept more data.
The DMA write block gets the destination address from its command FIFO and starts writing until
the specified number of bytes are transferred. If the data FIFO ever empties, the write block pauses
until the FIFO has more data to write.
• In memory-to-stream configurations, the DMA read block reads from the source address and
transfers the data to the core’s streaming port until the specified number of bytes are transferred or
the end of packet is reached. The block uses the end-of-packet indicator for transfers with an
unknown transfer size. For data transfers without using the end-of-packet indicator, the transfer
size must be a multiple of the data width. Otherwise, the block requires extra logic and may impact
the system performance.
• In stream-to-memory configurations, the DMA write block reads from the core’s streaming port
and writes to the destination address. The block continues reading until the specified number of
bytes are transferred.
5. The descriptor processor block receives a status from the DMA read or write block and updates the
DESC_CONTROL
,
DESC_STATUS
, and
ACTUAL_BYTES_TRANSFERRED
fields in the descriptor. The
OWNED_BY_HW
bit in the
DESC_CONTROL
field is cleared unless the
PARK
bit is set to 1.
Once the core starts processing the descriptors, software must not update descriptors with
OWNED_BY_HW
bit set to 1. It is only safe for software to update a descriptor when its
OWNED_BY_HW
bit is
cleared.
The SG-DMA core continues processing the descriptors until an error condition occurs and the
STOP_DMA_ER
bit is set to 1, or a descriptor with a cleared
OWNED_BY_HW
bit is encountered.
Building and Updating Descriptor List
Altera recommends the following method of building and updating the descriptor list:
1. Build the descriptor list and terminate the list with a non-hardware owned descriptor (
OWNED_BY_HW
=
0). The list can be arbitrarily long.
2. Set the interrupt
IE_CHAIN_COMPLETED
.
3. Write the address of the first descriptor in the first list to the
next_descriptor_pointer
register and
set the
RUN
bit to 1 to initiate transfers.
4. While the core is processing the first list, build a second list of descriptors.
5. When the SD-DMA controller core finishes processing the first list, an interrupt is generated. Update
the
next_descriptor_pointer
register with the address of the first descriptor in the second list. Clear
the
RUN
bit and the
status
register. Set the
RUN
bit back to 1 to resume transfers.
6. If there are new descriptors to add, always add them to the list which the core is not processing. For
example, if the core is processing the first list, add new descriptors to the second list and so forth.
This method ensures that the descriptors are not updated when the core is processing them. Because
the method requires a response to the interrupt, a high-latency interrupt may cause a problem in
systems where stalling data movement is not possible.
Error Conditions
The SG-DMA core has a configurable error width. Error signals are connected directly to the Avalon-ST
source or sink to which the SG-DMA core is connected.
UG-01085
2014.24.07
Error Conditions 21-7
Scatter-Gather DMA Controller Core Altera Corporation
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