Mailbox core, Core overview, Functional description – Altera Embedded Peripherals IP User Manual
Page 264: Mailbox core -1, Core overview -1, Functional description -1

Mailbox Core
27
2014.24.07
UG-01085
Multiprocessor environments can use the mailbox core with Avalon
®
interface to send messages between
processors.
The mailbox core contains mutexes to ensure that only one processor modifies the mailbox contents at a
time. The mailbox core must be used in conjunction with a separate shared memory that is used for
storing the actual messages.
The mailbox core is designed for use in Avalon-based processor systems, such as a Nios
®
II processor
system. Altera provides device drivers for the Nios II processor.
Core Overview
Multiprocessor environments can use the mailbox core with Avalon
®
interface to send messages between
processors.
The mailbox core contains mutexes to ensure that only one processor modifies the mailbox contents at a
time. The mailbox core must be used in conjunction with a separate shared memory that is used for
storing the actual messages.
The mailbox core is designed for use in Avalon-based processor systems, such as a Nios
®
II processor
system. Altera provides device drivers for the Nios II processor.
Functional Description
The mailbox core has a simple Avalon Memory-Mapped (Avalon-MM) slave interface that provides
access to four memory-mapped, 32-bit registers.
Table 27-1: Mutex Core Register Map
Offset
Register Name
R/W
Bit Description
31 16
15 1
0
0
mutex0
RW
OWNER
VALUE
1
reset0
RW
Reserved
RESET
2
mutex1
RW
OWNER
VALUE
3
reset1
RW
Reserved
RESET
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