Altera Embedded Peripherals IP - Manual (Page 153)

Field
Name
Description
REGAD/
Data
The register address (
REGAD
) or data field is 16 bits. For an address cycle, it contains the
address of the register to be accessed on the next cycle. For the data cycle of a write
frame, the field contains the data to be written to the register. For a read frame, the field
contains the contents of the register. The first bit transmitted and received is bit 15.
Idle
The idle condition on MDIO is a high-impedance state. All tri-state drivers are disabled
and the MMDs pullup resistor pulls the MDIO line to a one.
MDIO Clock Generation
The MDIO core’s MDC is generated from the Avalon-MM interface clock signal,
clk
. The
MDC_DIVISOR
parameter specifies the division parameter. For more information about the parameter, refer to the
Parameter section.
The division factor must be defined such that the MDC frequency does not exceed 2.5 MHz.
Interfaces
The MDIO core consists of a single Avalon-MM slave interface. The slave interface performs Avalon-MM
read and write transfers initiated by an Avalon-MM master in the client application logic. The Avalon-
MM slave uses the
waitrequest
signal to implement backpressure on the Avalon-MM master for any
read or write operation which has yet to be completed.
For more information about Avalon-MM interfaces, refer to the
Avalon Interface Specifications .
Operation
The MDIO core has bidirectional external signals to transfer data between the external PHY and the core.
Write Operation
Follow the steps below to perform a write operation.
1. Issue a write to the device register at address offset
0x21
to configure the device, port, and register
addresses of the PHY.
2. Issue a write to the
MDIO_ACCESS
register at address offset
0x20
to generate an MDIO frame and write
the data to the selected PHY device’s register.
Read Operation
Follow the steps below to perform a read operation.
UG-01085
2014.24.07
MDIO Clock Generation 15-3
MDIO Core Altera Corporation
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