Altera Embedded Peripherals IP - Manual (Page 235)

Transfer Size
The parameter Width of the DMA Length Register specifies the minimum width of the DMA’s transac‐
tion length register, which can be between 1 and 32. The
length
register determines the maximum
number of transfers possible in a single DMA transaction.
By default, the length register is wide enough to span any of the slave peripherals mastered by the read or
write ports. Overriding the length register may be necessary if the DMA master port (read or write)
masters only data peripherals, such as a UART. In this case, the address span of each slave is small, but a
larger number of transfers may be desired per DMA transaction.
Burst Transactions
When Enable Burst Transfers is turned on, the DMA controller performs burst transactions on its
master read and write ports. The parameter Maximum Burst Size determines the maximum burst size
allowed in a transaction.
In burst mode, the length of a transaction must not be longer than the configured maximum burst size.
Otherwise, the transaction must be performed as multiple transactions.
FIFO Depth
The parameter Data Transfer FIFO Depth specifies the depth of the FIFO buffer used for data transfers.
Altera recommends that you set the depth of the FIFO buffer to at least twice the maximum read latency
of the slave interface connected to the read master port. A depth that is too low reduces transfer
throughput.
FIFO Implementation
This option determines the implementation of the FIFO buffer between the master read and write ports.
Select Construct FIFO from Registers to implement the FIFO using one register per storage bit. This
option has a strong impact on logic utilization when the DMA controller’s data width is large. See the
Advanced Options section.
To implement the FIFO using embedded memory blocks available in the FPGA, select Construct FIFO
from Memory Blocks.
Advanced Options
The Advanced Options page includes the following parameters.
Allowed Transactions
You can choose the transfer datawidth(s) supported by the DMA controller hardware. The following
datawidth options can be enabled or disabled:
• Byte
• Halfword (two bytes)
• Word (four bytes)
• Doubleword (eight bytes)
• Quadword (sixteen bytes)
Disabling unnecessary transfer widths reduces the number of on-chip logic resources consumed by the
DMA controller core. For example, if a system has both 16-bit and 32-bit memories, but the DMA
controller transfers data to the 16-bit memory, 32-bit transfers could be disabled to conserve logic
resources.
23-4 Advanced Options
UG-01085
2014.24.07
Altera Corporation DMA Controller Core
Send Feedback