Altera Embedded Peripherals IP - Manual (Page 138)

This Avalon-MM master port is optimized for low latency access from PCI-to-Avalon-MM slaves. This is
optimal for providing PCI target access to simple Avalon-MM peripherals.
I/O Avalon-MM Master
The I/O Avalon-MM master port provides a low latency PCI I/O request access to Avalon-MM slave
peripherals. Burst operations are not supported on this master port. As only the exact amount of data
needed to service the initial data phase is read from the interconnect, the PCI byte enables (for the first
data phase of the PCI read transaction) are passed directly to the interconnect.
This Avalon-MM master port is also optimized for I/O access from PCI-to-Avalon-MM slaves for
providing PCI target access to simple Avalon-MM peripherals.
PCI Bus Access Slave
The Avalon bridge comprises up to five predefined ports to communicate with the interconnect
(depending on device operating mode).
This section discusses the five Avalon-MM ports:
• Single cycle memory read and write requests
• Burst memory read and write requests
• I/O read and write requests
• Configuration read and write requests
Burst requests from the interconnect are the only way to create burst transactions on the PCI bus.
This slave port is not implemented in the PCI Target-Only Peripheral mode.
Control Register Access (CRA) Avalon-MM Slave
This Avalon-MM slave port is used to access control registers in the PCI-Avalon bridge. To provide
external PCI master access to these registers, one of the bridge's master ports must be connected to this
port. There is no internal access inside the bridge from the PCI bus to these registers. You can only write
to these registers from the interconnect. The
Control Register Access Avalon Slave
port is only
enabled on Master/Target selection. The range of values supported by PCI CRA is 0x1000 to 0x1FFF.
Depending on the system design, these values can be accessed by PCI processors, Avalon processors or
both.
The table below shows the instructions on how to use these values. The address translation table is
writable via the
Control Register Access Avalon Slave
port. If the Number of Address Pages field is
set to the maximum of 512,
0x1FF8
contains
A2P_ADDR_MAP_LO511
and
0x1FFC
contains
A2P_ADDR_MAP_HI511
.
Each entry in the PCI address translation table is always 8 bytes wide. The lower order address bits that
are treated as a pass through between Avalon-MM and PCI, and the number of pass-through bits, are
defined by the size of page in the address translation table and are always forced to
0
in the hardware
table. For example, if the page size is 4 KBytes, the number of pass-through bits is log
2
(page size) = log
2
(4 KBytes) = 12.
Refer to
Avalon-to-PCI Address Translation for more details.
14-4 I/O Avalon-MM Master
UG-01085
2014.24.07
Altera Corporation PCI Lite Core
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