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Write fifo settings, Read fifo settings, Simulation settings – Altera Embedded Peripherals IP User Manual

Page 61: Simulated input character stream, Prepare interactive windows, Simulation settings -4

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Write FIFO Settings

The write FIFO buffers data flowing from the Avalon interface to the host. The following settings are

available:
Depth—The write FIFO depth can be set from 8 to 32,768 bytes. Only powers of two are allowed.

Larger values consume more on-chip memory resources. A depth of 64 is generally optimal for

performance, and larger values are rarely necessary.

IRQ Threshold—The write IRQ threshold governs how the core asserts its IRQ in response to the

FIFO emptying. As the JTAG circuitry empties data from the write FIFO, the core asserts its IRQ when

the number of characters remaining in the FIFO reaches this threshold value. For maximum

bandwidth, a processor should service the interrupt by writing more data and preventing the write

FIFO from emptying completely. A value of 8 is typically optimal. See the Interrupt Behavior section

for further details.

Construct using registers instead of memory blocks—Turning on this option causes the FIFO to be

constructed out of on-chip logic resources. This option is useful when memory resources are limited.

Each byte consumes roughly 11 logic elements (LEs), so a FIFO depth of 8 (bytes) consumes roughly

88 LEs.

Read FIFO Settings

The read FIFO buffers data flowing from the host to the Avalon interface. Settings are available to control

the depth of the FIFO and the generation of interrupts.
Depth—The read FIFO depth can be set from 8 to 32,768 bytes. Only powers of two are allowed.

Larger values consume more on-chip memory resources. A depth of 64 is generally optimal for

performance, and larger values are rarely necessary.

IRQ Threshold—The IRQ threshold governs how the core asserts its IRQ in response to the FIFO

filling up. As the JTAG circuitry fills up the read FIFO, the core asserts its IRQ when the amount of

space remaining in the FIFO reaches this threshold value. For maximum bandwidth, a processor

should service the interrupt by reading data and preventing the read FIFO from filling up completely.

A value of 8 is typically optimal. See the Interrupt Behavior section for further details.

Construct using registers instead of memory blocks—Turning on this option causes the FIFO to be

constructed out of logic resources. This option is useful when memory resources are limited. Each byte

consumes roughly 11 LEs, so a FIFO depth of 8 (bytes) consumes roughly 88 LEs.

Simulation Settings

At system generation time, when Qsys generates the logic for the JTAG UART core, a simulation model is

also constructed. The simulation model offers features to simplify simulation of systems using the JTAG

UART core. Changes to the simulation settings do not affect the behavior of the core in hardware; the

settings affect only functional simulation.

Simulated Input Character Stream

You can enter a character stream that will be simulated entering the read FIFO upon simulated system

reset. The MegaWizard Interface accepts an arbitrary character string, which is later incorporated into the

test bench. After reset, this character string is pre-initialized in the read FIFO, giving the appearance that

an external JTAG terminal program is sending a character stream to the JTAG UART core.

Prepare Interactive Windows

At system generation time, the JTAG UART core generator can create ModelSim

®

macros to open

interactive windows during simulation. These windows allow the user to send and receive ASCII

7-4

Write FIFO Settings

UG-01085

2014.24.07

Altera Corporation

JTAG UART Core

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