Altera Embedded Peripherals IP - Manual (Page 302)

The performance counter core can have up to seven section counters.
Global Counter
The global counter controls all section counters. The section counters are enabled only when the global
counter is running.
The 64-bit global clock cycle counter tracks the aggregate time for which the counters were enabled. The
32-bit global event counter tracks the number of global events, that is, the number of times the perform‐
ance counter core has been enabled.
Register Map
The performance counter core has an Avalon Memory-Mapped (Avalon-MM) slave interface that
provides access to memory-mapped registers. Reading from the registers retrieves the current times and
event counts. Writing to the registers starts, stops, and resets the counters.
Table 31-1: Performance Counter Core Register Map
Offset Register Name
Bit Description
Read Write
31 ... 0 31 ... 1 0
0
T[0] lo
global clock cycle counter [31: 0] (1) 0 =
STOP
1 =
RESET
1
T[0] hi
global clock cycle counter [63:32] (1) 0 =
START
2
Ev[0]
global event counter (1) (1)
3 — (1) (1) (1)
4
T[1] lo
section 1 clock cycle counter [31:0] (1) 0 =
STOP
5
T[1] hi
section 1 clock cycle counter [63:32] (1) 0 =
START
6
Ev[1]
section 1 event counter (1) (1)
7 — (1) (1) (1)
8
T[2] lo
section 2 clock cycle counter [31:0] (1) 0 =
STOP
9
T[2] hi
section 2 clock cycle counter [63:32] (1) 0 =
START
10
Ev[2]
section 2 event counter (1) (1)
11 — (1) (1) (1)
31-2 Global Counter
UG-01085
2014.24.07
Altera Corporation Performance Counter Core
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