Altera Embedded Peripherals IP - Manual (Page 81)

Some registers and bits are optional. These registers and bits exists in hardware only if it was enabled at
system generation time. Optional registers and bits are noted in the following sections.
rxdata Register
The
rxdata
register holds data received via the
RXD
input. When a new character is fully received via the
RXD
input, it is transferred into the
rxdata
register, and the
status
register's
rrdy
bit is set to 1. The
status
register's
rrdy
bit is set to 0 when the
rxdata
register is read. If a character is transferred into the
rxdata
register while the
rrdy
bit is already set (in other words, the previous character was not retrieved),
a receiver-overrun error occurs and the
status
register's
roe
bit is set to 1. New characters are always
transferred into the
rxdata
register, regardless of whether the previous character was read. Writing data
to the
rxdata
register has no effect.
txdata Register
Avalon-MM master peripherals write characters to be transmitted into the
txdata
register. Characters
should not be written to
txdata
until the transmitter is ready for a new character, as indicated by the
TRDY
bit in the
status
register. The
TRDY
bit is set to 0 when a character is written into the
txdata
register. The
TRDY
bit is set to 1 when the character is transferred from the
txdata
register into the transmitter shift
register. If a character is written to the
txdata
register when
TRDY
is 0, the result is undefined. Reading the
txdata
register returns an undefined value.
For example, assume the transmitter logic is idle and an Avalon-MM master peripheral writes a first
character into the
txdata
register. The
TRDY
bit is set to 0, then set to 1 when the character is transferred
into the transmitter shift register. The master can then write a second character into the
txdata
register,
and the
TRDY
bit is set to 0 again. However, this time the shift register is still busy shifting out the first
character to the
TXD
output. The
TRDY
bit is not set to 1 until the first character is fully shifted out and the
second character is automatically transferred into the transmitter shift register.
status Register
The
status
register consists of individual bits that indicate particular conditions inside the UART core.
Each status bit is associated with a corresponding interrupt-enable bit in the
control
register. The
status
register can be read at any time. Reading does not change the value of any of the bits. Writing zero to the
status
register clears the
DCTS
,
E
,
TOE
,
ROE
,
BRK
,
FE
, and
PE
bits.
Table 8-7: status Register Bits
Bit Name Access Description
0
(1
)
PE
RC Parity error. A parity error occurs when the received parity bit has an
unexpected (incorrect) logic level. The
PE
bit is set to 1 when the core
receives a character with an incorrect parity bit. The
PE
bit stays set to 1
until it is explicitly cleared by a write to the
status
register. When the
PE
bit is set, reading from the
rxdata
register produces an undefined value.
If the Parity hardware option is not enabled, no parity checking is
performed and the
PE
bit always reads 0. Refer to Data Bits, Stop, Bits,
Parity section.
1
FE
RC Framing error. A framing error occurs when the receiver fails to detect a
correct stop bit. The
FE
bit is set to 1 when the core receives a character
with an incorrect stop bit. The
FE
bit stays set to 1 until it is explicitly
cleared by a write to the
status
register. When the
FE
bit is set, reading
from the
rxdata
register produces an undefined value.
8-12 rxdata Register
UG-01085
2014.24.07
Altera Corporation UART Core
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