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Interrupt Behavior......................................................................................................................... 12-7
Software Files..................................................................................................................................12-7
Document Revision History.....................................................................................................................12-8
Avalon-ST Serial Peripheral Interface Core.....................................................13-1
Core Overview............................................................................................................................................13-1
Functional Description............................................................................................................................. 13-1
Interfaces.........................................................................................................................................13-1
Operation........................................................................................................................................ 13-2
Timing............................................................................................................................................. 13-2
Limitations......................................................................................................................................13-3
Configuration............................................................................................................................................. 13-3
Document Revision History.....................................................................................................................13-3
PCI Lite Core..................................................................................................... 14-1
Core Overview............................................................................................................................................14-1
Performance and Resource Utilization...................................................................................................14-1
Functional Description............................................................................................................................. 14-2
PCI-Avalon Bridge Blocks............................................................................................................14-2
Avalon-MM Ports..........................................................................................................................14-3
Prefetchable Avalon-MM Master................................................................................................ 14-3
Non-Prefectchable Avalon-MM Master.....................................................................................14-3
I/O Avalon-MM Master................................................................................................................14-4
PCI Bus Access Slave.....................................................................................................................14-4
Control Register Access (CRA) Avalon-MM Slave...................................................................14-4
Master and Target Performance.................................................................................................. 14-5
PCI-to-Avalon Address Translation........................................................................................... 14-6
Avalon-to-PCI Address Translation........................................................................................... 14-6
Avalon-To-PCI Read and Write Operation...............................................................................14-8
Ordering of Requests.....................................................................................................................14-9
PCI Interrupt................................................................................................................................14-10
Configuration...........................................................................................................................................14-10
PCI Timing Constraint Files...................................................................................................... 14-12
Simulation Considerations.....................................................................................................................14-13
Master Transactor (mstr_tranx)................................................................................................14-14
Simulation Flow........................................................................................................................... 14-15
Document Revision History...................................................................................................................14-16
MDIO Core........................................................................................................15-1
Functional Description............................................................................................................................. 15-1
MDIO Frame Format (Clause 45)...............................................................................................15-2
MDIO Clock Generation.............................................................................................................. 15-3
Interfaces.........................................................................................................................................15-3
Operation........................................................................................................................................ 15-3
Parameter....................................................................................................................................................15-4
Configuration Registers............................................................................................................................ 15-4
TOC-6
Altera Corporation
