Sdram controller core, Core overview, Functional description – Altera Embedded Peripherals IP User Manual
Page 17: Sdram controller core -1, Core overview -1, Functional description -1
SDRAM Controller Core
2
2014.24.07
UG-01085
Core Overview
The SDRAM controller core with Avalon
®
interface provides an Avalon Memory-Mapped (Avalon-MM)
interface to off-chip SDRAM. The SDRAM controller allows designers to create custom systems in an
Altera
®
device that connect easily to SDRAM chips. The SDRAM controller supports standard SDRAM as
described in the PC100 specification.
SDRAM is commonly used in cost-sensitive applications requiring large amounts of volatile memory.
While SDRAM is relatively inexpensive, control logic is required to perform refresh operations, open-row
management, and other delays and command sequences. The SDRAM controller connects to one or more
SDRAM chips, and handles all SDRAM protocol requirements. Internal to the device, the core presents an
Avalon-MM slave port that appears as linear memory (flat address space) to Avalon-MM master
peripherals.
The core can access SDRAM subsystems with various data widths (8, 16, 32, or 64 bits), various memory
sizes, and multiple chip selects. The Avalon-MM interface is latency-aware, allowing read transfers to be
pipelined. The core can optionally share its address and data buses with other off-chip Avalon-MM tri-
state devices. This feature is valuable in systems that have limited I/O pins, yet must connect to multiple
memory chips in addition to SDRAM.
Functional Description
The diagram below shows a block diagram of the SDRAM controller core connected to an external
SDRAM chip.
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