Mutex core, Core overview, Functional description – Altera Embedded Peripherals IP User Manual
Page 258: Mutex core -1, Core overview -1, Functional description -1
Mutex Core
26
2014.24.07
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Core Overview
Multiprocessor environments can use the mutex core with Avalon
®
interface to coordinate accesses to a
shared resource. The mutex core provides a protocol to ensure mutually exclusive ownership of a shared
resource.
The mutex core provides a hardware-based atomic test-and-set operation, allowing software in a
multiprocessor environment to determine which processor owns the mutex. The mutex core can be used
in conjunction with shared memory to implement additional interprocessor coordination features, such
as mailboxes and software mutexes.
The mutex core is designed for use in Avalon-based processor systems, such as a Nios
®
II processor
system. Altera provides device drivers for the Nios II processor to enable use of the hardware mutex.
Functional Description
The mutex core has a simple Avalon Memory-Mapped (Avalon-MM) slave interface that provides access
to two memory-mapped, 32-bit registers.
Table 26-1: Mutex Core Register Map
Offset
Register Name
R/W
Bit Description
31 16
15 1
0
0
mutex
RW
OWNER
VALUE
1
reset
RW
Reserved
RESET
The mutex core has the following basic behavior. This description assumes there are multiple processors
accessing a single mutex core, and each processor has a unique identifier (ID).
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