Altera Embedded Peripherals IP - Manual (Page 76)

speed, or roughly one character per 20 clock cycles. You can choose one of the following options for the
simulated transmitter baud rate:
• Accelerated (use divisor = 2)—
TXD
emits one bit per 2 clock cycles in simulation.
• Actual (use true baud divisor)—
TXD
transmits at the actual baud rate, as determined by the
divisor
register.
Simulation Considerations
The simulation features were created for easy simulation of Nios II processor systems when using the
ModelSim simulator. The documentation for the processor documents the suggested usage of these
features. Other usages may be possible, but will require additional user effort to create a custom
simulation process.
The simulation model is implemented in the UART core's top-level HDL file; the synthesizable HDL and
the simulation HDL are implemented in the same file. The simulation features are implemented using
translate on
and
translate off
synthesis directives that make certain sections of HDL code visible
only to the synthesis tool.
Do not edit the simulation directives if you are using Altera's recommended simulation procedures. If you
do change the simulation directives for your custom simulation flow, be aware that Qsys overwrites
existing files during system generation. Take precaution so that your changes are not overwritten.
For details about simulating the UART core in Nios II processor systems, refer to
AN 351: Simulating
Nios II Processor Designs .
Software Programming Model
The following sections describe the software programming model for the UART core, including the
register map and software declarations to access the hardware. For Nios II processor users, Altera
provides hardware abstraction layer (HAL) system library drivers that enable you to access the UART
core using the ANSI C standard library functions, such as
printf()
and
getchar()
.
HAL System Library Support
The Altera-provided driver implements a HAL character-mode device driver that integrates into the HAL
system library for Nios II systems. HAL users should access the UART via the familiar HAL API and the
ANSI C standard library, rather than accessing the UART registers.
ioctl()
requests are defined that
allow HAL users to control the hardware-dependent aspects of the UART.
Note: If your program uses the HAL device driver to access the UART hardware, accessing the device
registers directly interferes with the correct behavior of the driver.
For Nios II processor users, the HAL system library API provides complete access to the UART core's
features. Nios II programs treat the UART core as a character mode device, and send and receive data
using the ANSI C standard library functions.
The driver supports the CTS/RTS control signals when they are enabled in Qsys. Refer to Driver Options:
Fast Versus Small Implementations section.
The following code demonstrates the simplest possible usage, printing a message to
stdout
using
printf()
. In this example, the system contains a UART core, and the HAL system library has been
configured to use this device for
stdout
.
UG-01085
2014.24.07
Simulation Considerations 8-7
UART Core Altera Corporation
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