Interval timer core, Core overview, Functional description – Altera Embedded Peripherals IP User Manual
Page 249: Interval timer core -1, Core overview -1, Functional description -1, The interval timer core with avalon, Figure 25-1: interval timer core block diagram
Interval Timer Core
25
2014.24.07
UG-01085
Core Overview
The Interval Timer core with Avalon
®
interface is an interval timer for Avalon-based processor systems,
such as a Nios
®
II processor system. The core provides the following features:
• 32-bit and 64-bit counters.
• Controls to start, stop, and reset the timer.
• Two count modes: count down once and continuous count-down.
• Count-down period register.
• Option to enable or disable the interrupt request (IRQ) when timer reaches zero.
• Optional watchdog timer feature that resets the system if timer ever reaches zero.
• Optional periodic pulse generator feature that outputs a pulse when timer reaches zero.
• Compatible with 32-bit and 16-bit processors.
Device drivers are provided in the HAL system library for the Nios II processor.
Functional Description
Figure 25-1: Interval Timer Core Block Diagram
Register File
status
control
period_
n
snap_
n
IRQ
Address &
Data
Avalon-MM
slave interface
to on-chip
logic
Control
Logic
resetrequest
(watchdog)
timeout_pulse
Counter
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