Altera Embedded Peripherals IP - Manual (Page 2)

Contents
Introduction........................................................................................................ 1-1
Tool Support.................................................................................................................................................1-1
Obsolescence.................................................................................................................................................1-1
Device Support............................................................................................................................................. 1-2
Document Revision History.......................................................................................................................1-2
SDRAM Controller Core.....................................................................................2-1
Core Overview..............................................................................................................................................2-1
Functional Description............................................................................................................................... 2-1
Avalon-MM Interface......................................................................................................................2-2
Off-Chip SDRAM Interface............................................................................................................2-2
Board Layout and Pinout Considerations.................................................................................... 2-3
Performance Considerations..........................................................................................................2-4
Configuration............................................................................................................................................... 2-4
Memory Profile Page.......................................................................................................................2-5
Timing Page......................................................................................................................................2-6
Hardware Simulation Considerations.......................................................................................................2-7
SDRAM Controller Simulation Model......................................................................................... 2-7
SDRAM Memory Model.................................................................................................................2-7
Example Configurations............................................................................................................................. 2-8
Software Programming Model...................................................................................................................2-9
Clock, PLL and Timing Considerations................................................................................................... 2-9
Factors Affecting SDRAM Timing................................................................................................ 2-9
Symptoms of an Untuned PLL.....................................................................................................2-10
Estimating the Valid Signal Window..........................................................................................2-10
Example Calculation......................................................................................................................2-11
Document Revision History.....................................................................................................................2-13
Tri-State SDRAM................................................................................................ 3-1
Feature Description..................................................................................................................................... 3-1
Block Diagram..................................................................................................................................3-2
Configuration Parameter............................................................................................................................3-2
Memory Profile Page.......................................................................................................................3-2
Timing Page......................................................................................................................................3-2
Interface.........................................................................................................................................................3-3
Reset and Clock Requirements.................................................................................................................. 3-8
Architecture.................................................................................................................................................. 3-8
Avalon-MM Slave Interface and CSR........................................................................................... 3-9
Block Level Usage Model................................................................................................................ 3-9
Document Revision History.....................................................................................................................3-10
TOC-2
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