Spi core, Core overview, Functional description – Altera Embedded Peripherals IP User Manual
Page 107: Spi core -1, Core overview -1, Functional description -1
SPI Core
10
2014.24.07
UG-01085
Core Overview
SPI is an industry-standard serial protocol commonly used in embedded systems to connect
microprocessors to a variety of off-chip sensor, conversion, memory, and control devices. The SPI core
with Avalon
®
interface implements the SPI protocol and provides an Avalon Memory-Mapped (Avalon-
MM) interface on the back end.
The SPI core can implement either the master or slave protocol. When configured as a master, the SPI
core can control up to 32 independent SPI slaves. The width of the receive and transmit registers are
configurable between 1 and 32 bits. Longer transfer lengths can be supported with software routines. The
SPI core provides an interrupt output that can flag an interrupt whenever a transfer completes.
Functional Description
The SPI core communicates using two data lines, a control line, and a synchronization clock:
• Master Out Slave In (
mosi
)—Output data from the master to the inputs of the slaves
• Master In Slave Out (
miso
)—Output data from a slave to the input of the master
• Serial Clock (
sclk
)—Clock driven by the master to slaves, used to synchronize the data bits
• Slave Select (
ss_n
)— Select signal (active low) driven by the master to individual slaves, used to select
the target slave
The SPI core has the following user-visible features:
• A memory-mapped register space comprised of five registers:
rxdata
,
txdata
,
status
,
control
, and
slaveselect
• Four SPI interface ports:
sclk
,
ss_n
,
mosi
, and
miso
The registers provide an interface to the SPI core and are visible via the Avalon-MM slave port. The
sclk
,
ss_n
,
mosi
, and
miso
ports provide the hardware interface to other SPI devices. The behavior of
sclk
,
ss_n
,
mosi
, and
miso
depends on whether the SPI core is configured as a master or slave.
©
2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at
www.altera.com/common/legal.html
. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134