Altera Embedded Peripherals IP - Manual (Page 294)

Avalon-ST JTAG Interface Core
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Functional Description
The figure below shows a block diagram of the Avalon-ST JTAG Interface core in a typical system
configuration.
Figure 29-1: System with an Avalon-ST JTAG Interface Core
Avalon-ST
Source
Avalon-ST
Sink
Avalon-ST
JTAG Interface
Core
System
Clock JTAG
Clock
G
AT
J
a
F t
c
e
n
n
o
cr
et
nI
m
et
s
y
S
b
cir
Rest of the
System
data_out
data_in
JTAG
Host
(System
Console)
Altera FPGA
resetrequest
Interfaces
Table 29-1: Properties of Avalon-ST Interfaces
Feature Property
Backpressure Only supported on the sink interface.
Data Width Data width = 8 bits; Bits per symbol = 8.
Channel Not supported.
Error Not used.
Packet Not supported.
For more information about Avalon-ST interfaces, refer to the Avalon Interface Specifications .
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