Avalon-mm slave interface and csr, Block level usage model, Avalon-mm slave interface and csr -9 – Altera Embedded Peripherals IP User Manual
Page 39: Block level usage model -9
Avalon-MM Slave Interface and CSR
The host processor perform data read and write operation to the external SDRAM devices through the
Avalon-MM interface of the SDRAM core.
Please refer to Avalon Interface Specifications for more information on
the details of the Avalon-MM Slave Interface.
Block Level Usage Model
Figure 3-2: Shared-Bus System
UG-01085
2014.24.07
Avalon-MM Slave Interface and CSR
3-9
Tri-State SDRAM
Altera Corporation
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