Altera interrupt latency counter, Overview, Altera interrupt latency counter -1 – Altera Embedded Peripherals IP User Manual
Page 329: Overview -1
Altera Interrupt Latency Counter
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Overview
A processor running a program can be instructed to divert from its original execution path by an
interrupt signal generated either by peripheral hardware or the firmware that is currently being executed.
The processor now executes the portions of the program code that handles the interrupt requests known
as Interrupt Service Routines (ISR) by moving to the instruction pointer to the ISR, and then continues
operation. Upon completion of the routine, the processor returns to the previous location.
Altera’s Interrupt Latency Calculator (ILC) is developed in mind to measure the time taken in terms of
clock cycles to complete the interrupt service routine. Data obtained from the ILC is utilized by other
latency sensitive IPs in order for it to maintain its proper operation. The data from the ILC can also be
used to help the general firmware debugging exercise.
The Interrupt Latency Calculator sits as a parallel to any interrupt receiver that will consume and perform
an interrupt service routine. The following figure shows the orientation of a Interrupt Latency Calculator
in a system design.
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