Altera Embedded Peripherals IP - Manual (Page 26)

• Timing parameters of the device and SDRAM I/O pins — I/O timing parameters vary based on device
family and speed grade.
• Pin location on the device — I/O pins connected to row routing have different timing than pins
connected to column routing.
• Logic options used during the Quartus II compilation — Logic options such as the Fast Input Register
and Fast Output Register logic affect the design fit. The location of logic and registers inside the
device affects the propagation delays of signals to the I/O pins.
• SDRAM CAS latency
As a result, the valid window timing is different for different combinations of FPGA and SDRAM
devices. The window depends on the Quartus II software fitting results and pin assignments.
Symptoms of an Untuned PLL
Detecting when the PLL is not tuned correctly might be difficult. Data transfers to or from the SDRAM
might not fail universally. For example, individual transfers to the SDRAM controller might succeed,
whereas burst transfers fail. For processor-based systems, if software can perform read or write data to
SDRAM, but cannot run when the code is located in SDRAM, the PLL is probably tuned incorrectly.
Estimating the Valid Signal Window
This section describes how to estimate the location and duration of the valid signal window using timing
parameters provided in the SDRAM datasheet and the Quartus II software compilation report. After
finding the window, tune the PLL so that SDRAM clock edges occur exactly in the middle of the window.
Calculating the window is a two-step process. First, determine by how much time the SDRAM clock can
lag the controller clock, and then by how much time it can lead. After finding the maximum lag and lead
values, calculate the midpoint between them.
These calculations provide an estimation only. The following delays can also affect proper PLL tuning, but
are not accounted for by these calculations.
• Signal skew due to delays on the printed circuit board — These calculations assume zero skew.
• Delay from the PLL clock output nodes to destinations — These calculations assume that the delay
from the PLL SDRAM-clock output-node to the pin is the same as the delay from the PLL controller-
clock output-node to the clock inputs in the SDRAM controller. If these clock delays are significantly
different, you must account for this phase shift in your window calculations.
Lag is a negative time shift, relative to the controller clock, and lead is a positive time shift. The
SDRAM clock can lag the controller clock by the lesser of the maximum lag for a read cycle or that for
a write cycle. In other words, Maximum Lag = minimum(Read Lag, Write Lag). Similarly, the SDRAM
clock can lead by the lesser of the maximum lead for a read cycle or for a write cycle. In other words,
Maximum Lead = minimum(Read Lead, Write Lead).
2-10 Symptoms of an Untuned PLL
UG-01085
2014.24.07
Altera Corporation SDRAM Controller Core
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