Altera Embedded Peripherals IP - Manual (Page 129)

After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those
PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional
mode, to change the direction of the PIO port, reprogram the
direction
register.
interruptmask Register
Setting a bit in the
interruptmask
register to 1 enables interrupts for the corresponding PIO input port.
Interrupt behavior depends on the hardware configuration of the PIO core. See the Interrupt Behavior
section.
The
interruptmask
register only exists when the hardware is configured to generate IRQs. If the core
cannot generate IRQs, reading
interruptmask
returns an undefined value, and writing to
interrupt-
mask
has no effect.
After reset, all bits of
interruptmask
are zero, so that interrupts are disabled for all PIO ports.
edgecapture Register
Bit n in the
edgecapture
register is set to 1 whenever an edge is detected on input port n. An Avalon-MM
master peripheral can read the
edgecapture
register to determine if an edge has occurred on any of the
PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any
value to the
edgecapture
register clears all bits in the register. Otherwise, writing a 1 to a particular bit in
the register clears only that bit.
The type of edge(s) to detect is fixed in hardware at system generation time. The
edgecapture
register
only exists when the hardware is configured to capture edges. If the core is not configured to capture
edges, reading from
edgecapture
returns an undefined value, and writing to
edgecapture
has no effect.
outset and outclear Register
You can use the
outset
and
outclear
registers to set and clear individual bits of the output port. For
example, to set bit 6 of the output port, write
0x40
to the
outset
register. Writing
0x08
to the
outclear
register clears bit 3 of the output port.
These registers are only present when the option Enable individual bit set/clear output register is turned
on.
Interrupt Behavior
The PIO core outputs a single IRQ signal that can connect to any master peripheral in the system. The
master can read either the
data
register or the
edgecapture
register to determine which input port
caused the interrupt.
When the hardware is configured for level-sensitive interrupts, the IRQ is asserted whenever
corresponding bits in the
data
and
interruptmask
registers are 1. When the hardware is configured for
edge-sensitive interrupts, the IRQ is asserted whenever corresponding bits in the
edgecapture
and
interruptmask
registers are 1. The IRQ remains asserted until explicitly acknowledged by disabling the
appropriate bit(s) in
interruptmask
, or by writing to
edgecapture
.
Software Files
The PIO core is accompanied by the following software file. This file provide low-level access to the
hardware. Application developers should not modify the file.
•
altera_avalon_pio_regs.h —This file defines the core's register map, providing symbolic constants to
access the low-level hardware. The symbols in this file are used by device driver functions.
UG-01085
2014.24.07
interruptmask Register 12-7
PIO Core Altera Corporation
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