Altera Embedded Peripherals IP - Manual (Page 23)

Settings Allowe
d
Values
Default
Value
Description
Write recovery
time (t_wr, No
auto precharge)
— 14 ns Write recovery if explicit precharge commands are
issued. This SDRAM controller always issues explicit
precharge commands.
Regardless of the exact timing values you specify, the actual timing achieved for each parameter is an
integer multiple of the Avalon clock period. For the Issue one refresh command every parameter, the
actual timing is the greatest number of clock cycles that does not exceed the target value. For all other
parameters, the actual timing is the smallest number of clock ticks that provides a value greater than or
equal to the target value.
Hardware Simulation Considerations
This section discusses considerations for simulating systems with SDRAM. Three major components are
required for simulation:
• A simulation model for the SDRAM controller.
• A simulation model for the SDRAM chip(s), also called the memory model.
• A simulation testbench that wires the memory model to the SDRAM controller pins.
Some or all of these components are generated by Qsys at system generation time.
SDRAM Controller Simulation Model
The SDRAM controller design files generated by Qsys are suitable for both synthesis and simulation.
Some simulation features are implemented in the HDL using “translate on/off” synthesis directives that
make certain sections of HDL code invisible to the synthesis tool.
The simulation features are implemented primarily for easy simulation of Nios and Nios II processor
systems using the ModelSim ® simulator. The SDRAM controller simulation model is not ModelSim
specific. However, minor changes may be required to make the model work with other simulators.
If you change the simulation directives to create a custom simulation flow, be aware that Qsys overwrites
existing files during system generation. Take precautions to ensure your changes are not overwritten.
Refer to
AN 351: Simulating Nios II Processor Designs for a demonstration of simulation of the
SDRAM controller in the context of Nios II embedded processor systems.
SDRAM Memory Model
This section describes the two options for simulating a memory model of the SDRAM chip(s).
Using the Generic Memory Model
If the Include a functional memory model the system testbench option is enabled at system generation,
Qsys generates an HDL simulation model for the SDRAM memory. In the auto-generated system
testbench, Qsys automatically wires this memory model to the SDRAM controller pins.
Using the automatic memory model and testbench accelerates the process of creating and verifying
systems that use the SDRAM controller. However, the memory model is a generic functional model that
does not reflect the true timing or functionality of real SDRAM chips. The generic model is always
UG-01085
2014.24.07
Hardware Simulation Considerations 2-7
SDRAM Controller Core Altera Corporation
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