Altera Embedded Peripherals IP - Manual (Page 299)

Configuration
The
id
and
timestamp
register values are determined at system generation time based on the
configuration of the Qsys system and the current time. You can add only one system ID core to an Qsys
system, and its name is always
sysid
.
After system generation, you can examine the values stored in the
id
and
timestamp
registers by opening
the MegaWizard ™ interface for the System ID core. Hovering the mouse over the component in Qsys also
displays a tool-tip showing the values.
Since a unique
timestamp
value is added to the System ID HDL file each time you generate the Qsys
system, the Quartus II software recompiles the entire system if you have added the system as a design
partition.
Software Programming Model
This section describes the software programming model for the system ID core. For Nios II processor
users, Altera provides the HAL system library header file that defines the System ID core registers.
The System ID core comes with the following software files. These files provide low-level access to the
hardware. Application developers should not modify these files.
•
alt_avalon_sysid_regs.h —Defines the interface to the hardware registers.
• alt_avalon_sysid.c, alt_avalon_sysid.h —Header and source files defining the hardware access functions.
Altera provides one access routine,
alt_avalon_sysid_test()
, that returns a value indicating
whether the system ID expected by software matches the system ID core.
alt_avalon_sysid_test()
Prototype: alt_32 alt_avalon_sysid_test(void)
Thread-safe: No.
Available
from ISR:
Yes.
Include:
Description: Returns 0 if the values stored in the hardware registers match the values expected
by software. Returns 1 if the hardware timestamp is greater than the software
timestamp. Returns -1 if the software timestamp is greater than the hardware
timestamp.
30-2 Configuration
UG-01085
2014.24.07
Altera Corporation System ID Core
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