Altera Embedded Peripherals IP - Manual (Page 332)

Counter Stop Registers
Table 34-4: Counter Stop Registers
Field Name Counter Stop Registers
Bit Location 31 0
If the ILC is configured to support the pulse IRQ signal, then the counter stop registers are utilized by
running software to halt the counter. Each bit corresponds to the IRQ port. For example, bit 0 controls
IRQ_0
counter. To stop the counter you have to write a binary ‘1’ into the register. Counter stop registers
do not affect the operation of the ILC in level mode.
Note: You need to clear the counter stop register to properly capture the next round of IRQ delay.
Latency Data Registers
Table 34-5: Latency Data Registers
Field Name Latency Data Registers
Bit Location 31 0
The latency data registers holdthe latency value in terms of clock cycle from the moment the interrupt
signal is fired until the IRQ signal goes low for level configuration or counter stop register being set for
pulse configuration. This is a 32-bit read only register with each address corresponding to one IRQ port.
The latency data registers can only be read three clock cycles after the IRQ signal goes low or when the
counter stop registers are set to high in the level and pulse operating mode, respectively.
Data Valid Registers
Table 34-6: Data Valid Registers
Field Name Data Valid Registers
Bit Location 31 0
The data valid registers indicate whether the data from the latency data regsters are ready to be read or
not. By default, these registers hold a binary value of ‘0’ out of reset. Once the counter data is transfered to
the latency data register, the corresponding bit within the data valid register is set to binary '1'. It reverts
back to binary ‘0’ after a read operation has been consumed by the ILC. The values of these registers
determines whether the Interrupt Latency IP back pressures an incoming command through the
waitrequest signal.
32-bit Counter
The 32-bit positive edge triggered D-flop base up counter takes in a reset signal which clears all the
registers to zero. It also has an enable signal that determines when the counter operation is turned on or
off.
34-4 Counter Stop Registers
UG-01085
2014.24.07
Altera Corporation Altera Interrupt Latency Counter
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