Altera Embedded Peripherals IP - Manual (Page 161)

FIFO Settings
The following sections outline the settings that pertain to the FIFO core as a whole.
Depth
Depth indicates the depth of the FIFO buffer, in Avalon-ST beats or Avalon-MM words. The default
depth is 16. When dual clock mode is used, the actual FIFO depth is equal to depth-3. This is due to clock
crossing and to avoid FIFO overflow.
Clock Settings
The two options are Single clock mode and Dual clock mode. In Single clock mode, all interface ports
use the same clock. In Dual clock mode, input data and input side status are on the input clock domain.
Output data and output side status are on the output clock domain.
Status Port
The optional status ports are Avalon-MM slaves. To include the optional input side status interface, turn
on Create status interface for input on the Qsys MegaWizard. For FIFOs whose input and output ports
operate in separate clock domains, you can include a second status interface by turning on Create status
interface for output. Turning on Enable IRQ for status ports adds an interrupt signal to the status ports.
FIFO Implementation
This option determines if the FIFO core is built from registers or embedded memory blocks. The default
is to construct the FIFO core from embedded memory blocks.
Interface Parameters
The following sections outline the options for the input and output interfaces.
Input
Available input interfaces are Avalon-MM write slave and Avalon-ST sink.
Output
Available output interfaces are Avalon-MM read slave and Avalon-ST source.
Allow Backpressure
When Allow backpressure is on, an Avalon-MM interface includes the
waitrequest
signal which is
asserted to prevent a master from writing to a full FIFO buffer or reading from an empty FIFO buffer. An
Avalon-ST interface includes the
ready
and
valid
signals to prevent underflow and overflow conditions.
Avalon-MM Port Settings
Valid Data widths are 8, 16, and 32 bits.
If Avalon-MM is selected for one interface and Avalon-ST for the other, the data width is fixed at 32 bits.
The Avalon-MM interface accesses data 4 bytes at a time. For data widths other than 32 bits, be careful of
potential overflow and underflow conditions.
16-6 FIFO Settings
UG-01085
2014.24.07
Altera Corporation On-Chip FIFO Memory Core
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