Altera Embedded Peripherals IP User Manual
Page 195
Descriptor Processor
The descriptor processor reads descriptors from the descriptor list via its Avalon
®
Memory-Mapped
(MM) read master port and pushes commands into the command FIFOs of the DMA read and write
blocks. Each command includes the following fields to specify a transfer:
• Source address
• Destination address
• Number of bytes to transfer
• Increment read address after each transfer
• Increment write address after each transfer
• Generate start of packet (SOP) and end of packet (EOP)
After each command is processed by the DMA read or write block, a status token containing informa‐
tion about the transfer such as the number of bytes actually written is returned to the descriptor
processor, where it is written to the respective fields in the descriptor.
DMA Read Block
The DMA read block is used in memory-to-memory and memory-to-stream configurations. The block
performs the following operations:
• Reads commands from the input command FIFO.
• Reads a block of memory via the Avalon-MM read master port for each command.
• Pushes data into the data FIFO.
If burst transfer is enabled, an internal read FIFO with a depth of twice the maximum read burst size is
instantiated. The DMA read block initiates burst reads only when the read FIFO has sufficient space to
buffer the complete burst.
DMA Write Block
The DMA write block is used in memory-to-memory and stream-to-memory configurations. The block
reads commands from its input command FIFO. For each command, the DMA write block reads data
from its Avalon-ST sink port and writes it to the Avalon-MM master port.
If burst transfer is enabled, an internal write FIFO with a depth of twice the maximum write burst size is
instantiated. Each burst write transfers a fixed amount of data equals to the write burst size, except for the
last burst. In the last burst, the remaining data is transferred even if the amount of data is less than the
write burst size.
Memory-to-Memory Configuration
Memory-to-memory configurations include all three blocks: descriptor processor, DMA read, and DMA
write. An internal FIFO is also included to provide buffering and flow control for data transferred
between the DMA read and write blocks.
The example below illustrates one possible memory-to-memory configuration with an internal Nios II
processor and descriptor list.
21-4
Functional Blocks and Configurations
UG-01085
2014.24.07
Altera Corporation
Scatter-Gather DMA Controller Core