Altera modular scatter-gather dma, Overview, Feature description – Altera Embedded Peripherals IP User Manual
Page 217: Altera modular scatter-gather dma -1, Overview -1, Feature description -1
Altera Modular Scatter-Gather DMA
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2014.24.07
UG-01085
Overview
In a processor subsystem, data transfers between two memory spaces can happen frequently. In order to
offload the processor from moving data around a system, a Direct Memory Access (DMA) engine can be
introduced to perform this function instead. The Modular Scatter-Gather DMA (mSGDMA) is capable of
performing data movement operations with preloaded instructions, called descriptors. Multiple descrip‐
tors with different transfer sizes, and source and destination addresses are supported with the option to
trigger interrupts.
The mSGDMA has a modular design that facilitates easy integration with the FPGA fabric. It consists of a
dispatcher block with optional read master and write master blocks. The descriptor block receives and
decodes the descriptor and dispatches instructions to the read master and write master blocks for further
operation. It can also be configured to transfer additional information to the host. In this context, the read
master block reads data via its Avalon-MM master interface and channels it into Avalon-ST source
interface based on instruction given by dispatcher block. On the other hand, the write master block
receives data from its Avalon-ST sink interface and write it to the destination address via its Avalon-MM
master interface.
Feature Description
Altera mSGDMA provides three configuration structures for handling data transfers between Avalon-
MM to Avalon-MM, Avalon-MM to Avalon-ST, and Avalon-ST to Avalon-MM modes. Sub-core of
mSGDMA are instantiated automatically according to the structure configured for mSGDMA use model.
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